DP600 Memory Chip

Interface Protocol

●Support PCle 4.0 single/dual channel

●Support PCle dual port

●Support SR-IOV (up to 64 VFs)

●Support NVMe1.4a, NVMe MI 1.1

●Up to 32 NameSpaces are supported

Performance

●Sequential read 14GB/s, sequential write 10GB/s

●Random read 2.1M IOPS

●Random write 700KIOPS (continuous, OP 20%)

●4K random write latency is less than 5μs

Flash type

●Support SLC/MLC/TLC/3D-TLC/QL CIXL-Flash to absorb Toggle/ONFI flash

●Support two mixed Flash types (such as QLC&SLC)

●16-channel single I/0 speed up to 1600MTSS (ONFI4.2)

Data integrity

●DDR4/3 DRAM with ECC (1 bit can be corrected every 32/64 bits)

●Support DIF/DIX protection (external and internal)

●Full internal data path protection (DPP)

●SRAM storage data protection (ECC or CRC)

●Super LDPC 4KB code error correction capability

●Hardware RAID5 protection

●Enhanced power-down protection

●End-to-end data protection

●Built-in temperature sensor and monitor chip junction temperature

Safety

●Support TCG/AES/RSA/SHA/TRNG

●Support SM2/SM3/SM4

● Secure Boot

●Support FPGA/ASIC specific encryption algorithm

Capacity expansion

●32TB @ single DP600

●Capacity cascade DP600 controller

Storage Management

● On-chip RNN neural network (LSTM)

●Smart 10/SmartECC technology